View ADN4600_8355221.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4.25 gbps , 8 8 , asynchronous crosspoint switch d ata sheet ADN4600 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents o r other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are t he property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2008 C 2012 analog devices, inc. all rights reserved. technical support www.analog.com features full 8 8 crossbar connectivity fully buffered signal path supports multicast and broadcast operation optimized for dc to 4.25 gbps data programmable receive equalization compensates for up to 3 0 in. of fr4 @ 4.25 gbps programmable transmit pre - e mphasis/de - emphasis compensates for up to 3 0 in . of fr4 @ 4.25 gbps flexible 1.8 v to 3.3 v core supply per lane positive/negative (p/n) pair inversion for routing ease low power: 125 mw/channel at 4.25 gbps dc - or ac - coupled differential cml inputs progr ammable cml output levels 50 ? on - chip termination ?40 c to +85c temperature range operation supports 8b10b, scrambled or uncoded nonreturn - to - zero (nrz) data i 2 c control interface package: 64 - lead lfcsp applications 1 , 2 , 4 fibrechannel xaui gigabit ethernet over backplane 10gbase - cx4 infini b and ? 50 ? cables functional block dia gram receive equalization crosspoint array transmit pre-emphasis control logic ADN4600 ip[7:0] in[7:0] addr[1:0] scl sda resetb op[7:0] on[7:0] 07061-001 eq pe figure 1. general description the ADN4600 is an asynchronous , non blocking crosspoint switch with eight differential pecl - /cml - comp atible inputs with programmable equalization and eight differential cml outputs with programmable output levels and pre - emphasis or de - emphasis. the operation of this device is optimized for nrz data at rates up to 4.25 gbps. the receive inputs provide pr ogrammable equalization with nine settings to compensate for up to 3 0 in. of fr4 and programmable pre - emphasis with seven settings to compensate for up to 3 0 in. of fr4 at 4.25 gbps. the a dn4600 non blocking switch core implements an 8 8 crossbar and sup ports independent channel switching through the i 2 c control interface. every channel implements an asynchronous path supporting nrz data rate s from dc to 4.25 gbps. each channel is fully independent of other channels. the ADN4600 has low latency and very l ow channel - to - channel skew. the main application for the ADN4600 is to support switching on the backplane, line card, or cable interface sides of serial links. the ADN4600 is packaged in a 9 mm 9 mm, 64- lead lfcsp package and operates from ? 40c to +85c.
ADN4600 data sheet rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functio nal block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 spe cifications ..................................................................................... 3 electrical specifications ............................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ..............................................8 theory of operation ...................................................................... 13 introduction ................................................................................ 13 receivers ...................................................................................... 13 switch core ................................................................................. 15 transmitters ................................................................................ 16 i 2 c control interface .................................................................. 22 pcb design guidelines ............................................................. 24 control register map ..................................................................... 25 package outline dimensions ........................................................ 28 ordering guide .......................................................................... 28 revision history 1 2 /12 rev. 0 to rev. a changes to table 16 ........................................................................ 25 changes to ordering guide .......................................................... 28 6/08 rev ision 0: initial version
d ata sheet ADN4600 rev. a | page 3 of 28 specifications electrical specifica tions v cc = 1.8 v, v ee = 0 v, v tti = v tto = v cc , r l = 50 , differential output swing = 800 mv p - p differential , 4.25 gbps, prbs 2 7 ? 1, t a = 25c , unless otherwise noted. table 1 . parameter conditions min typ max unit dynamic performance max imum data rate per channel in nrz forma t 4.25 gbps deterministic jitter data rate < 4.25 gbps; ber = 1e ? 12 30 ps p -p random jitter v cc = 1.8 v 1.5 ps rms residual deterministic jitter with receive equalization data rate < 3.25 gbps; 0 in. to 30 in. fr4 0.16 ui data rate < 4.25 g bps; 0 in. to 30 in. fr4 0.20 ui residual deterministic jitter with transmit pre - emphasis data rate < 3.25 gbps; 0 in. to 30 in. fr4 0.13 ui data rate < 4.25 gbps; 0 in. to 30 in. fr4 0.18 ui output rise/fall time 20% to 80% 75 ps channel - to - channel skew 50 ps propagation delay 1 n s output pre - emphasis equalization method one - tap programmable pre - emphasis maximum boost 800 mv p - p output swing 6 db 200 mv p - p output swing 12 db pre - emphasis tap range minimum 2 ma maximum 12 ma input equalization minimum boost eqby = 1 1.5 db maximum boost maximum boost occurs @ 2.125 ghz 22 db number of equalization steps 8 steps gain step size 2.5 db input characteristics input voltage swing differe ntial, v icm 1 = v cc ? 0.6 v; v cc = 3.3 v 3 00 2000 mv p -p input voltage range single - ended absolute voltage level, v l minimum v ee + 0.4 v p -p single - ended absolute voltage level, v h maximum v cc + 0.5 v p -p input resistance single - ended 45 50 55 input return loss m easured at 2.5 ghz 5 db output characteristics output voltage swing @ dc, differential, pe = 0, default, v cc = 1.8 v 635 740 870 mv p -p @ dc, differential, pe = 0, default, v cc = 3.3 v 800 mv p -p @ dc, differential, pe = 0, min output level 2 , v cc = 1.8 v 100 mv p -p @ dc, differential, pe = 0, min output level 2 , v cc = 3.3 v 100 mv p -p @ dc, differential, pe = 0, max output level 2 , v cc = 1.8 v 1300 mv p -p @ dc, differ ential, pe = 0, max output level 2 , v cc = 3.3 v 1800 mv p -p output voltage range single - ended absolute voltage level, txheadroom = 0; v l min v cc ? 1.1 v single - ended absolute voltage level, txheadroom = 0; v h max v cc + 0.6 v single - ended absolute voltage level, txheadroom = 1; v l min v cc ? 1.2 v single - ended absolute voltage level, txheadroom = 1; v h max v cc + 0.6 v output current minimum output current per channel 2 ma maximum output current per ch annel, v cc = 1.8 v 21 output resistance single ended 45 50 55 output return loss measured at 2.5 ghz 5 db
ADN4600 data sheet rev. a | page 4 of 28 parameter conditions min typ max unit power supply operating range v cc v ee = 0 v 1.7 1.8 3.6 v dv cc v ee = 0 v, dv cc (v cc + 1.3 v) 3.0 3.3 3.6 v v tti (v ee + 0.4 v + 0.5 v id ) < v tti < (v cc + 0.5 v) v ee + 0.4 1.8 3.6 v v tto (v cc ? 1.1 v + 0.5 v od ) < v tto < (v cc + 0.5 v) v cc ? 1.1 1.8 3.6 v supply current 3 i tto all outputs enabled 63 69 ma i cc all outputs enabled 460 565 ma i ee all outputs enabled 586 ma i tto single channel enabled 16 18 ma i cc single channel enabled 173 214 ma i ee single channel enabled 205 ma logic characteristics input high (v ih ) dvcc = 3.3 v 2.5 v input low (v il ) 1.0 v output high (v oh ) 2.5 v output low (v ol ) 1.0 v thermal characteristics operating temperature range ?40 +85 c ja 22 c/w 1 v icm is the input common - mode voltage. 2 programmable via i 2 c. 3 assumes dc - coupled outputs. for ac - coupled outputs, i tto currents will double.
ADN4600 rev. 0 | page 5 of 5 timing specifications table 2. i 2 c timing parameters parameter min max unit description f scl 0 400 khz scl clock frequency t hd;sta 0.6 n/a s hold time for a start condition t su;sta 0.6 n/a s setup time for a repeated start condition t low 1.3 n/a s low period of the scl clock t high 0.6 n/a s high period of the scl clock t hd;dat 0 n/a s data hold time t su;dat 10 n/a ns data setup time t r 1 300 ns rise time for both sda and scl t f 1 300 ns fall time for both sda and scl t su;sto 0.6 n/a s setup time for a stop condition t buf 1 n/a ns bus-free time between a stop and a start condition c io 5 7 pf capacitance for each i/o pin i 2 c timing specifications 07061-010 s p sr s sda scl t f t f t f t f t buf t low t hd:sta t hd:dat t high t su:dat t su:sta t su:sto t hd:sta figure 2. i 2 c timing diagram
ADN4600 data sheet rev. a | page 6 of 28 absolute maximum rat ings table 3 . parameter rating v cc to v ee 3.7 v v tti v cc + 0.6 v v tto v cc + 0.6 v internal power dissipation 4.26 w differential input voltage 2.0 v logic input voltage v ee ? 0.3 v < v in < v cc + 0.6 v storage temperature range ?65 c to +125 c lead temperature 300 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at t hese or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
d ata sheet ADN4600 rev. a | page 7 of 28 pin configuration and function description s 07061-002 pin 1 indic a t or 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vee vcc on7 op7 vcc on6 op6 vtt o on5 op5 vee on4 op4 vee vcc vee 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vee vcc vee op0 on0 vcc op1 on1 vtt o op2 on2 vee op3 on3 addr1 addr0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 resetb vee in0 ip0 vcc in1 ip1 vtti in2 ip2 vee in3 ip3 dvcc vcc vee scl sda vee ip7 in7 vcc ip6 in6 vtti ip5 in5 vee ip4 in4 vcc vee 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ADN4600 top view (not to scale) notes 1. pad on bottom of package must be connected to vee. figure 3. pin configuration table 4 . pin function descriptions pin no. mnemonic type description 1 resetb control reset input ( active low ) 2 , 11, 16, 17, 27, 30, 32, 33, 37, 46, 53, 62, 64 vee power negative supply 3 , 6, 9, 12, 35, 38, 41, 44 in0 to in7 i/o high speed input s 4 , 7, 10, 13, 36, 39, 42, 45 ip0 to ip7 i/o high speed input complement s 5 , 15, 18, 21, 31, 34, 43, 59, 63 vcc power positive supply 8 , 40 vtti power input t ermination supply 14 dvcc power digital positive supply (3.3 v) 19 , 22, 25, 28, 51, 54, 57, 60 on7 to on0 i/o high speed output s 20 , 23, 26, 29, 52, 55, 58, 61 op7 to on0 i/o high speed output complement s 24 , 56 vtto power output termination supply 47 sda control i 2 c control interface data input/output 48 scl control i 2 c control interface clock input 49 addr0 control i 2 c control interface address lsb 50 addr1 control i 2 c control interface address msb epad power connect to vee
ADN4600 data sheet rev. a | page 8 of 28 typical performance characteristics figure 5 to figure 8 were obtained using the standard test circuit shown in figure 4 . 50? cables 2 2 high speed sampling oscilloscope 50? cables 2 2 50? ADN4600 ac-coupled evaluation board input pin output pin pattern generator data out tp2 tp1 07061-011 figure 4 . standard test circuit (no channel) 07061-012 50ps/div 200mv/div figure 5 . 3.25 gbps input eye (tp1 from figure 4) 07061-013 50ps/div 200mv/div figure 6. 4.2 5 gbps input eye (tp1 from figure 4) 07061-014 50ps/div 200mv/div figure 7 . 3.25 g bps output eye, no channel (tp2 from figure 4) 07061-015 50ps/div 200mv/div figure 8. 4.2 5 gbps output eye, no channel (tp2 from figure 4)
d ata sheet ADN4600 rev. a | page 9 of 28 figure 10 to figure 13 were obtained using the standard test circuit shown in figure 9 . 50? cables 2 2 tp3 high speed sampling oscilloscope 50? cables 2 2 50? ADN4600 ac-coupled evaluation board input pin output pin pattern generator data out tp1 50? cables 2 2 tp2 fr4 test backplane differential stripline traces 8mils wide, 8mils space, 8mils dielectric height trace lengths = 30'' 07061-016 figure 9 . input equalization test circuit, fr4 (see figure 5 and figure 6 for the reference eye diagram s at tp1) 07061-017 50ps/div 200mv/div figure 10 . 3.25 gbps input eye, 3 0 inch fr4 input channel (tp2 from figure 9) 07061-018 50ps/div 200mv/div figure 11 . 4.25 gbps input eye, 3 0 inch fr4 input channel (tp2 from figure 9) 07061-019 50ps/div 200mv/div figure 12 . 3.25 gbps output eye, 3 0 inch fr4 input channel, best eq setting (tp3 from figure 9) 07061-020 50ps/div 200mv/div figure 13 . 4.25 gbps output eye, 3 0 inch fr4 input channel, best eq setting (tp3 from figure 9)
ADN4600 data sheet rev. a | page 10 of 28 figure 15 to figure 18 were obtained using the standard test circuit shown in figure 14. 50? cables 2 2 tp3 high speed sampling oscilloscope 50? cables 2 2 50? ADN4600 ac-coupled evaluation board input pin output pin pattern generator data out tp1 50? cables 2 2 tp2 07061-021 fr4 test backplane differential stripline traces 8mils wide, 8mils space, 8mils dielectric height trace lengths = 30'' figure 14 . outpu t pre - emphasis test circuit, fr4 07061-022 50ps/div 200mv/div figure 15 . 3.25 gbps output eye, 3 0 inch fr4 output channel, pe = 0 (tp3 from figure 14 ) 07061-023 50ps/div 200mv/div figure 16 . 4.25 gbps output eye, 3 0 inch fr4 output channel, pe = 0 (tp3 from figure 14 ) 07061-024 50ps/div 200mv/div figure 17 . 3.25 gbps output eye, 3 0 inch fr4 output channel, pe = best setting (tp3 from figure 14 ) 07061-025 50ps/div 200mv/div figure 18 . 4.2 5 gbps output eye, 3 0 inch fr4 output channel, pe = best setting (tp3 from figure 14 )
d ata sheet ADN4600 rev. a | page 11 of 28 te st conditions : v cc = 1.8 v, v ee = 0 v, v tti = v tto = v cc , r l = 50 , differential output swing = 800 mv p - p differential, t a = 25c, unless otherwise noted. 80 70 60 50 40 30 20 10 0 0 20 40 60 data rate (hz) deterministic jitter (ps) 07061-026 figure 19 . deterministic jitter vs. data rate 100 90 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 differential input swing (v) deterministic jitter (ps) 07061-027 figure 20 . deterministic jitter vs. input swing 100 80 60 40 20 0 ?60 ?40 ?20 0 20 40 60 80 100 temperature (c) deterministic jitter (ps) 07061-028 figure 21 . deterministic jitter vs. temperature 100 80 60 40 20 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 input common mode (v) deterministic jitter (ps) 07061-029 v cc = 3.3v v cc = 1.8v figure 22 . deterministic jitter vs. input common mode 100 80 60 40 20 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v cc (v) deterministic jitter (ps) 07061-030 figure 23 . deterministic jitter vs. supply voltage 100 80 60 40 20 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v tto (v) deterministic jitter (ps) 07061-031 v cc = 3.3v v cc = 1.8v figure 24 . deterministic jitter vs. output termination voltage
ADN4600 data sheet rev. a | page 12 of 28 450000 400000 350000 300000 250000 200000 150000 100000 50000 0 ?8 ?6 ?4 ?2 0 2 4 6 8 10 jitter (ps) number of samples 07061-032 figure 25 . random jitter histogram 100 90 80 70 60 50 ?60 ?40 ?20 0 20 40 60 80 100 temperature (c) t r /t f (ps) 07061-033 t r /t f figure 26 . rise time/fall time vs. temperature
d ata sheet ADN4600 rev. a | page 13 of 28 theory of operation introduction the ADN4600 is an 8 8 , buffered, asynchronous, 8 - channel crosspoint switch that allows fully non blocking connectivity between its transmitters and receivers. the switch supports m ulti cast and broadcast operation, allowing the ADN4600 to work in redundancy and port - replic ation applications. receive equalization crosspoint array transmit pre-emphasis control logic ADN4600 ip[7:0] in[7:0] addr[1:0] scl sda resetb op[7:0] on[7:0] 07061-003 eq pe figure 27 . simplified functional block diagram the ADN4600 offers extensively programmable output levels and pre - emphasis , as well as a squelch function and the ability to full y disable the device . the receive rs integrate a program mable, multi zero transfer function tha t has been optimized to compensate either typical backplane or typical cable losses. the ADN4600 provides a balanced, high speed switch core that maintains low channel - to - channel skew and preserve s edge rates. the i/o on - chip termination resistors are tied to user - settable supplies to support dc coupling in various logic styles . the ADN4600 supports a wide core supply range ; v cc can be set from 1.8 v to 3.3 v. these features together with programma ble transmitter outp ut levels allow for several dc - and ac - coupled i/o configurations. receivers input structure and input levels vcc vtti ipx inx vee simplified receiver input circuit rln rl rlp rl q1 q2 i1 r3 1k? r1 750? r2 750? rn 52? rp 52? 07061-004 figure 28 . simplified input structure the ADN4600 receiver inputs incorporate 50 termination resisto rs, esd protection, and a multi zero transfer function equalizer that can be optimized for backplane and cable operation. each receive channel also provides a positive/negative ( p/n ) inversion function , which allows the user to swap the sign of the input signal path to eliminate the need for board - level cross overs in the receiver channel. table 5 illustrates some, but not all, possible combinations of input supply voltages. equalization settings the adn460 0 receiver incorporates a multi zero transfer function with a continuous time equalizer , providing up to 2 2 db of high - frequency boost at 2.25 ghz to compensate for up to 3 0 in. of fr4 at 4.25 gbps. the ADN4600 also allows independent control of t he equalizer transfer function on each channel through the i 2 c control interface. in the basic mode of operation, t he equalizer transfer function allows independent control of the boost in two frequency ranges for optimal matching with the los s shape of th e channel (for example, the shape due primarily to skin effect or to dielectric loss). the total equalizer shape space is reduced to two independent frequency response groups one optimized for cable and the other optimized for fr4 material . the rx eq bits of the rx[7:0] configuration registers provide eight settings for each frequency response group to ease programming for typical channels. table 6 summarizes the high - frequency boost for the frequency response grou ping optimized for the fr4 material; it lists the basic control settings and the typical length of fr4 trace compensated for by each setting . all eight chan nels of the ADN4600 use the fr4 - optimized frequency response grouping by default. the user can overr ide this default by setting the respective rx lut select bit high and then selecting the frequency response grouping by setting the rx lut fr4/cx4 bit high for fr4 and low for cable. setting the rx eqby bit of the rx[7:0] configuration registers high sets the equalization to 1.5 db of boost , which compensates for 0 m to 2 m of cx4 or 0 in. to 10 in. of fr4. in the advanced mode of operation, full control of the equalizer is available through the i 2 c control interface. the user can specify the boost in the m id frequency range and the boost in the high frequency range independently. this is accomplished by circumventing the frequency response groupings shown in table 6 by setting the eq ctl src bit (bit 6 of the rx [7:0] eq1 control registers) high and writing dir ectly to the equalizer control bits on a per channel basis . therefore , write values to bits [5:0] of the rx [7:0] eq1 control register s and to bits [5:0] of the rx [7:0] eq3 control register s for the channel of inte rest. the bits of these registers are ordered such that bit 5 is a sign bit, and mid level boost is centered around 0x00 . s etting bit 5 low and increasing the lsbs decreases the boost, wh ereas setting bit 5 high and increasing the lsbs increas es the boost.
ADN4600 data sheet rev. a | page 14 of 28 table 5 . common input voltage levels configuration v cc (v) v tti (v) low v tti , ac - coupled input 1.8 1.6 single 1.8 v supply 1.8 1.8 3.3 v core 3.3 1.8 single 3.3 v supply 3.3 3.3 table 6 . receiv e equalizer boost vs. setting rx eq bit settings boost (db) typical fr4 trace length (inches) 0 3.5 5 to 10 1 3.9 10 to 15 2 4.25 15 to 20 3 4.5 20 to 25 4 4.75 25 to 30 5 5.0 30 to 35 6 5.3 35 to 40 7 5.5 35 to 40 table 7 . equalization control registers name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default rx [ 7:0 ] configuration 0xb8, 0xb0, 0xa8, 0xa0, 0x98, 0x90, 0x88, 0x80 rx pnswap rx eqby rx en rx eq [2] rx eq[1] rx eq[0] 0x30 rx [7:0 ] eq1 control 0xb b, 0xb3, 0xab, 0xa3, 0x9b, 0x93, 0x8b, 0x83 eq ctl src rx eq1 [5] rx eq1 [4] rx eq1 [3] rx eq1 [2] rx eq1 [1] rx eq1 [0] 0x00 rx [ 7:0 ] eq 3 control 0xbc, 0xb4, 0xac, 0xa4, 0x9c, 0x94, 0x8c, 0x84 rx eq 3 [5] rx eq 3 [4] rx eq 3 [3] rx eq 3 [2] rx eq 3 [1] rx eq 3 [0 ] 0x00 rx [ 7:0 ] fr4 control 0xbd, 0xb5, 0xad, 0xa5, 0x9d, 0x95, 0x8d, 0x85 rx lut select rx lut fr4/cx4 0x00 lane inversion the receiver p/n inversion feature is a convenience intended to allow the user to implement the eq uivalent of a boar d - level cross over in a much smaller area and without additional via impedance discontinuities that degrade the high - frequency integrity of the signal path. the p/n inversion is independent for each of the eight channels and is controlled through the i 2 c co ntrol interface. wa r ning using the lane inversion feature to account for signal inversions downstream of the receiver requires additional attention when switching connectivity.
d ata sheet ADN4600 rev. a | page 15 of 28 switch core the ADN4600 switch core is a fully non blocking 8 8 array that allows multi cast and broadcast configurations. the configuration of the switch core is controlled through the i 2 c control interface. the control interface receives and stores the desired connection matrix for the eight input and eight output signal pairs. the interface consists of eight rows of double - rank latches, one for each output. the 2 - bit data - word stored in these latches indicates to which (if any) of the eight inputs the output will be connected. one output at a time can be preprogrammed by addre ssing the output and writing the desired connection data into the first rank of latches. this is done by writing to the xpt config uration register (address 0x40). the output being addressed is written into bits [2:0] , and the input be ing sent to this output is written into bits [6:4]. this process can be repeated until each of the desired output changes has been preprogrammed. bit 3 of the xpt configuration register ( address 0x40) signals whether a b roadcast condition is desired. if this bit is set high , t he input selected by bits [6:4] is sent to all outputs. all output connections can then be programmed simultaneously by passing the data from the first rank of latches into the second rank by writing 0x01 to the xpt update register ( address 0x41). this is a self - clearing register and therefore always read s back as 0x00. the output connections always reflect the data programmed into the second rank of latches and do not change until the first rank of data is passed into the second rank by strobing the xpt upd ate register. if necessary for system verification, the data in the first rank of latches can be read back from the control interface. this is done by reading from the xpt te mp [3:0] registers, which show the status of the input data programmed in the first rank of latches for each output. table 8 . switch core control and status registers name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default xpt config uration 0x40 in port [ 2] in port [ 1] in port [ 0] broadcast out port [ 2] out port [ 1] out port [ 0] 0x00 xpt update 0x41 update 0x00 xpt status 0 0x50 out0 [ 2] out0 [ 1] out0 [ 0] n/a xpt status 1 0x51 out1 [ 2] out1 [ 1] out1 [ 0] n/a xpt status 2 0x52 out2 [ 2] out2 [ 1] out2 [ 0] n/a xpt status 3 0x53 out3 [ 2 ] out3 [ 1] out3 [ 0] n/a xpt status 4 0x54 out4 [ 2] out4 [ 1] out4 [ 0] n/a xpt status 5 0x55 out5 [ 2] out5 [ 1] out5 [ 0] n/a xpt status 6 0x56 out6 [ 2] out6 [ 1] out6 [ 0] n/a xpt status 7 0x57 out7 [ 2] out7 [ 1] out7 [ 0] n/a table 9 . switch core temp orary registers name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default xpt temp 0 0x58 out1 [ 2] out1 [ 1] out1 [ 0] out0 [ 2] out0 [ 1] out0 [ 0] n/a xpt temp 1 0x59 out3 [ 2] out3 [ 1] out3 [ 0] out2 [ 2] out2 [ 1] out2 [ 0] n/a xpt te mp 2 0x5a out5 [ 2] out5 [ 1] out5 [ 0] out4 [ 2] out4 [ 1] out4 [ 0] n/a xpt temp 3 0x5b out7 [ 2] out7 [ 1] out7 [ 0] out6 [ 2] out6 [ 1] out6 [ 0] n/a
ADN4600 data sheet rev. a | page 16 of 28 transmitters output structure and output levels the ADN4600 transmitter outputs incorporate 50 termination resistors, esd protection, and output current switch . each channel provides independent control of both the absolute output level and the pre - emphasis output level. it should be noted that the choice of output level affects the output common - mode level. a 600 mv p - p d ifferential output level with full pre - emphasis range requires an output terminati on voltage of 2.5 v or greater ; therefore, for the vtto pin , v cc must be equal to or greater than 2.5 v . pre - emphasis the total output amplitude a nd pre - emphasis setting space is reduced to a single map of basic settings that provides seven settings of output equalization to ease programming for typical channels. the full resolution of seven settings is available through the i 2 c interface by writing to bits[2:0] ( the tx pe[2:0] bits ) of the tx[7:0] configuration registers. table 10 summarizes the absolute output level, pre - emphasis level, and high frequency boost for each of the control settings and the typical length of fr4 tra ce compensated for by each setting . full control of the transmit output levels is available through the i 2 c control interface. this full control is achieved by writing to the tx[7:0] output level control[1:0] registers for the channel of interest. the supported output levels are shown in table 12. the tx[7:0] output level control[1:0] r egisters must be programmed to one of the supported settings listed in this table ; o ther settings are not supported. the output equalization i s optimized for less than 2. 5 gbps operation, but can be optimized for higher speed applications up to 4.2 5 gbps through the i 2 c control interface by writing to the tx data rate bit (bit 4) of the tx[7:0] configuration registe r , with high representing 4.2 5 gbps and low representing 2. 5 gbps. the tx[7:0] ctl src bit (bit 7) in the tx[7:0] output level control 1 register determines whether the pre - emphasis and output current controls for the channel of interest are selected from the optimized map or directly from the tx[7:0] output level control[1:0] registers (per channel). setting this bit high selects pre - emphasis control directly from the tx[7:0] output level control[1:0] registers, and setting it low selects pre - emphasis control from the optimized map. vcc vtto opx onx vee tx simplified diagram q1 q2 it rn 52? rp 52? on-chip termination v3 vc v2 vp v1 vn i dc + t pe 07061-006 esd figure 29 . simplified output structure table 10. transmit pre - emphasis boost and overshoot vs. setting tx pe boost (db) overshoot dc swing (mv p - p differential) typical fr4 trace length (inches) 0 0 0% 800 0 to 5 1 2 25% 800 0 to 5 2 3.5 50% 800 10 to 15 3 4.9 75% 800 15 to 20 4 6 100% 800 25 to 30 5 7.4 133% 600 30 to 35 6 9.5 200% 400 35 to 40 table 11. transmitters control registers name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 def . tx [ 7:0 ] configuration 0xe0, 0xe8, 0xf0, 0xf8, 0xd8, 0xd0, 0xc8, 0xc0 tx en tx data rate tx pe [ 2] tx pe [ 1] tx pe [ 0] 0x20 tx[7:0] output level control 1 0xe1, 0xe9, 0xf1, 0xf9, 0xd9, 0xd1, 0xc9, 0xc1 tx [7:0] ctl src tx [7:0]_ olev1[6:0] 0x40 tx[7:0] output level control 0 0xe2, 0xea, 0xf2, 0xfa, 0xda, 0xd2, 0xca, 0xc2 tx[7:0]_ olev0[6:0] 0x40
d ata sheet ADN4600 rev. a | page 17 of 28 table 12. output level programming v od (mv) v d peak (mv) pe (db) i tot (ma) tx[7:0] output level con trol 0 tx[7:0] output level control 1 50 50 0.00 2 0x00 0x81 50 150 9.54 6 0x11 0x81 50 250 13.98 10 0x22 0x81 50 350 16.90 14 0x33 0x81 50 450 19.08 18 0x44 0x81 50 550 20.83 22 0x55 0x81 50 650 22.28 26 0x66 0x81 100 100 0.00 4 0x00 0x91 100 200 6.02 8 0x11 0x91 100 300 9.54 12 0x22 0x91 100 400 12.04 16 0x33 0x91 100 500 13.98 20 0x44 0x91 100 600 15.56 24 0x55 0x91 100 700 16.90 28 0x66 0x91 150 150 0.00 6 0x00 0x92 150 250 4.44 10 0x11 0x92 150 350 7.36 14 0x22 0x92 150 450 9.54 18 0x 33 0x92 150 550 11.29 22 0x44 0x92 150 650 12.74 26 0x55 0x92 150 750 13.98 30 0x66 0x92 200 200 0.00 8 0x00 0xa2 200 300 3.52 12 0x11 0xa2 200 400 6.02 16 0x22 0xa2 200 500 7.96 20 0x33 0xa2 200 600 9.54 24 0x44 0xa2 200 700 10.88 28 0x55 0xa2 2 00 800 12.04 32 0x66 0xa2 250 250 0.00 10 0x00 0xa3 250 350 2.92 14 0x11 0xa3 250 450 5.11 18 0x22 0xa3 250 550 6.85 22 0x33 0xa3 250 650 8.30 26 0x44 0xa3 250 750 9.54 30 0x55 0xa3 250 850 10.63 34 0x66 0xa3 300 300 0.00 12 0x00 0xb3 300 400 2.50 16 0x11 0xb3 300 500 4.44 20 0x22 0xb3 300 600 6.02 24 0x33 0xb3 300 700 7.36 28 0x44 0xb3 300 800 8.52 32 0x55 0xb3 300 900 9.54 36 0x66 0xb3 350 350 0.00 14 0x00 0xb4 350 450 2.18 18 0x11 0xb4 350 550 3.93 22 0x22 0xb4 350 650 5.38 26 0x33 0xb4 350 750 6.62 30 0x44 0xb4 350 850 7.71 34 0x55 0xb4 350 950 8.67 38 0x66 0xb4 400 400 0.00 16 0x00 0xc4 400 500 1.94 20 0x11 0xc4 400 600 3.52 24 0x22 0xc4
ADN4600 data sheet rev. a | page 18 of 28 v od (mv) v d peak (mv) pe (db) i tot (ma) tx[7:0] output level con trol 0 tx[7:0] output level control 1 400 700 4.86 28 0x33 0xc4 400 800 6.02 32 0x44 0xc4 400 900 7.04 36 0x55 0xc4 400 1000 7. 96 40 0x66 0xc4 450 450 0.00 18 0x00 0xc5 450 550 1.74 22 0x11 0xc5 450 650 3.19 26 0x22 0xc5 450 750 4.44 30 0x33 0xc5 450 850 5.52 34 0x44 0xc5 450 950 6.49 38 0x55 0xc5 450 1050 7.36 42 0x66 0xc5 500 500 0.00 20 0x00 0xd5 500 600 1.58 24 0x11 0 xd5 500 700 2.92 28 0x22 0xd5 500 800 4.08 32 0x33 0xd5 500 900 5.11 36 0x44 0xd5 500 1000 6.02 40 0x55 0xd5 500 1100 6.85 44 0x66 0xd5 550 550 0.00 22 0x00 0xd6 550 650 1.45 26 0x11 0xd6 550 750 2.69 30 0x22 0xd6 550 850 3.78 34 0x33 0xd6 550 950 4.75 38 0x44 0xd6 550 1050 5.62 42 0x55 0xd6 550 1150 6.41 46 0x66 0xd6 600 600 0.00 24 0x00 0xe6 600 700 1.34 28 0x11 0xe6 600 800 2.50 32 0x22 0xe6 600 900 3.52 36 0x33 0xe6 600 1000 4.44 40 0x44 0xe6 600 1100 5.26 44 0x55 0xe6 600 1200 6.02 4 8 0x66 0xe6 650 650 0.00 26 0x01 0xe6 650 750 1.24 30 0x12 0xe6 650 850 2.33 34 0x23 0xe6 650 950 3.30 38 0x34 0xe6 650 1050 4.17 42 0x45 0xe6 650 1150 4.96 46 0x56 0xe6 700 700 0.00 28 0x02 0xe6 700 800 1.16 32 0x13 0xe6 700 900 2.18 36 0x24 0xe6 700 1000 3.10 40 0x35 0xe6 700 1100 3.93 44 0x46 0xe6 750 750 0.00 30 0x03 0xe6 750 850 1.09 34 0x14 0xe6 750 950 2.05 38 0x25 0xe6 750 1050 2.92 42 0x36 0xe6 800 800 0.00 32 0x04 0xe6 800 900 1.02 36 0x15 0xe6 800 1000 1.94 40 0x26 0xe6 850 850 0.00 34 0x05 0xe6 850 950 0.97 38 0x16 0xe6 900 900 0.00 36 0x06 0xe6
d ata sheet ADN4600 rev. a | page 19 of 28 high current setting and output level shift in low voltage applications, users must pay careful attention to both the differential and common - mode signal levels (see figure 30 and table 13 ). failure to understand the implications of signal level and choice of ac or dc coupling will almost certainly lead to transistor saturation and poor transmitter p erformance. txheadroom there is a txheadroom register (i 2 c register addr ess 0x23 ) that allows configuration of the individ ual transmitters for extra head room at the output for high current applications. the bits in this register are active high (default) . there is one bit for each transmitter of the device (see table 17) . setting this bit high puts the respective transmitter in a configuration for extra headroom , and setting this bit low does not provide extra headroom. vtto v h v ocm dv ocm v od v l vee 07061-007 v odpp = 2 v od figure 30 . simplified output voltage levels diagram signal levels and common - mode shift for dc - and ac - coupled outputs table 13. signal levels and common - mode shift for dc - and ac - coupled outputs output levels and output compliance ac - coupled transmitter dc - coupled transmitter txheadroom = 0 txheadroom = 1 v od (mv) i tot (ma) v d peak (mv) pe boost pe (db) dv ocm (mv) v h (v) v l (v) v h peak (v) v l peak (v) d v ocm (mv) v h (v) v l (v) v h peak (v) v l pe ak (v) min v l (v) max v cc ? v l (v) min v cc (v) min v l (v) max v cc ? v l (v) min v cc (v) v tto and v cc = 3.3 v 200 8 200 1.00 0.00 200 3.2 3 3.2 3 100 3.3 3.1 3.3 3.1 2.225 1.1 1.8 2 1.2 2 200 12 300 1.50 3.52 300 3.1 2.9 3.15 2.85 150 3.25 3.05 3.3 3 2.225 1.1 1.8 2 1.2 2 200 16 400 2.00 6.02 400 3 2.8 3.1 2.7 200 3.2 3 3.3 2.9 2.225 1.1 1.8 2 1.2 2 200 20 500 2.50 7.96 500 2.9 2.7 3.05 2.55 250 3.15 2.95 3.3 2.8 2.225 1.1 1.8 2 1.2 2 200 24 600 3.00 9.54 600 2.8 2.6 3 2.4 300 3.1 2.9 3.3 2.7 2.225 1.1 1.8 2 1.2 2 200 28 700 3.50 10.88 700 2.7 2.5 2.95 2.25 350 3.05 2.85 3.3 2.6 2.225 1.1 1.9 2 1.2 2.2 200 32 800 4.00 12.04 800 2.6 2.4 2.9 2.1 400 3 2.8 3.3 2.5 2.225 1.1 1.9 2 1.2 2.2 300 12 300 1.00 0.00 300 3.15 2.85 3.15 2.85 150 3.3 3 3.3 3 2.225 1.1 1.8 2 1.2 2 300 16 400 1.33 2.50 400 3.05 2.75 3.1 2.7 200 3.25 2.95 3.3 2.9 2.225 1.1 1.8 2 1.2 2 300 20 500 1.67 4.44 500 2.95 2.65 3.05 2.55 250 3.2 2.9 3.3 2.8 2.225 1.1 1.8 2 1.2 2 300 24 600 2.00 6.02 600 2.85 2.55 3 2.4 300 3.15 2.85 3.3 2.7 2.225 1.1 1.8 2 1.2 2 300 28 700 2.33 7.36 700 2.75 2.45 2.95 2.25 350 3.1 2.8 3.3 2.6 2.225 1.1 1.8 2 1.2 2 300 32 800 2.67 8.52 800 2.65 2.35 2.9 2.1 400 3.05 2.75 3.3 2.5 2.225 1.1 1.9 2 1.2 2.2 300 36 900 3.00 9.54 900 2.55 2.25 2.85 1.95 450 3 2.7 3.3 2.4 2.225 1.1 1 .9 2 1.2 2.2 400 16 400 1.00 0.00 400 3.1 2.7 3.1 2.7 200 3.3 2.9 3.3 2.9 2.225 1.1 1.8 2 1.2 2 400 20 500 1.25 1.94 500 3 2.6 3.05 2.55 250 3.25 2.85 3.3 2.8 2.225 1.1 1.8 2 1.2 2 400 24 600 1.50 3.52 600 2.9 2.5 3 2.4 300 3.2 2.8 3.3 2.7 2.225 1.1 1.8 2 1.2 2 400 28 700 1.75 4.86 700 2.8 2.4 2.95 2.25 350 3.15 2.75 3.3 2.6 2.225 1.1 1.8 2 1.2 2 400 32 800 2.00 6.02 800 2.7 2.3 2.9 2.1 400 3.1 2.7 3.3 2.5 2.225 1.1 1.8 2 1.2 2 400 36 900 2.25 7.04 900 2.6 2.2 2.85 1.95 450 3.05 2.65 3.3 2.4 2.225 1.1 1.9 2 1.2 2.2 400 40 1000 2.50 7.96 1000 2.5 2.1 2.8 1.8 500 3 2.6 3.3 2.3 2.225 1.1 1.9 2 1.2 2.2 600 24 600 1.00 0.00 600 3 2.4 3 2.4 300 3.3 2.7 3.3 2.7 2.1 1.1 1.9 2 1.2 2.2 600 28 700 1.17 1.34 700 2.9 2.3 2.95 2.25 350 3.25 2.65 3.3 2.6 2.225 1.1 1.9 2 1.2 2.2 600 32 800 1.33 2.50 800 2.8 2.2 2.9 2.1 400 3.2 2.6 3.3 2.5 2.225 1.1 1.9 2 1.2 2.2 600 36 900 1.50 3.52 900 2.7 2.1 2.85 1.95 450 3.15 2.55 3.3 2.4 2.225 1.1 1.9 2 1.2 2.2 600 40 1000 1.67 4.44 1000 2.6 2 2.8 1.8 500 3.1 2.5 3.3 2.3 2.2 25 1.1 1.9 2 1.2 2.2 600 44 1200 1.83 5.26 1100 2.5 1.9 2.75 1.65 550 3.05 2.45 3.3 2.2 2.1 1.1 1.9 2 1.2 2.2 600 48 1400 2.00 6.02 1200 2.4 1.8 2.7 1.5 600 3 2.4 3.3 2.1 2.1 1.1 1.9 2 1.2 2.2
ADN4600 data sheet rev. a | page 20 of 28 output levels and output compliance ac - coupled transmitter dc - coupled transmitter txheadroom = 0 txheadroom = 1 v od (mv) i tot (ma) v d peak (mv) pe boost pe (db) dv ocm (mv) v h (v) v l (v) v h peak (v) v l peak (v) d v ocm (mv) v h (v) v l (v) v h peak (v) v l pe ak (v) min v l (v) max v cc ? v l (v) min v cc (v) min v l (v) max v cc ? v l (v) min v cc (v) v tto and v cc = 1.8 v 1 200 8 200 1.00 0.00 200 1.7 1.5 1.7 1 .5 100 1.8 1.6 1.8 1.6 0.725 1.1 1.8 0.5 na na 200 12 300 1.50 3.52 300 1.6 1.4 1.65 1.35 150 1.75 1.55 1.8 1.5 0.725 1.1 1.8 0.5 na na 200 16 400 2.00 6.02 400 1.5 1.3 1.6 1.2 200 1.7 1.5 1.8 1.4 0.725 1.1 1.8 0.5 na na 200 20 500 2.50 7.96 500 1.4 1.2 1.55 1.05 250 1.65 1.45 1.8 1.3 0.725 1.1 1.8 0.5 na na 200 24 600 3.00 9.54 600 1.3 1.1 1.5 0.9 300 1.6 1.4 1.8 1.2 0.725 1.1 1.8 0.5 na na 300 12 300 1.00 0.00 300 1.65 1.35 1.65 1.35 150 1.8 1.5 1.8 1.5 0.725 1.1 1.8 0.5 na na 300 16 400 1.33 2.50 4 00 1.55 1.25 1.6 1.2 200 1.75 1.45 1.8 1.4 0.725 1.1 1.8 0.5 na na 300 20 500 1.67 4.44 500 1.45 1.15 1.55 1.05 250 1.7 1.4 1.8 1.3 0.725 1.1 1.8 0.5 na na 300 24 600 2.00 6.02 600 1.35 1.05 1.5 0.9 300 1.65 1.35 1.8 1.2 0.725 1.1 1.8 0.5 na na 300 28 7 00 2.33 7.36 700 1.25 0.95 1.45 0.75 350 1.6 1.3 1.8 1.1 0.725 1.1 1.8 0.5 na na 400 16 400 1.00 0.00 400 1.6 1.2 1.6 1.2 200 1.8 1.4 1.8 1.4 0.725 1.1 1.8 0.5 na na 400 20 500 1.25 1.94 500 1.5 1.1 1.55 1.05 250 1.75 1.35 1.8 1.3 0.725 1.1 1.8 0.5 na na 400 24 600 1.50 3.52 600 1.4 1 1.5 0.9 300 1.7 1.3 1.8 1.2 0.725 1.1 1.8 0.5 na na 400 28 700 1.75 4.86 700 1.3 0.9 1.45 0.75 350 1.65 1.25 1.8 1.1 0.725 1.1 1.8 0.5 na na 400 32 800 2.00 6.02 800 1.2 0.8 1.4 0.6 400 1.6 1.2 1.8 1 0.725 1.1 1.8 0.5 na na 600 24 600 1.00 0.00 600 1.5 0.9 1.5 0.9 300 1.8 1.2 1.8 1.2 0.6 1.1 1.9 0.5 na na 1 txheadroom = 1 is not an option at v tto and v cc = 1.8 v . table 14. symbol definitions for output levels vs. setting symbol formula definition v od 25 i dc peak differential output voltage v od pp 2 5 i dc 2 = 2 v od peak - to - peak differential output voltage d v ocm_dc - coupled 25 i tx /2 = v odpp /4 + (i pe /2 25) output common - mode shift d v ocm_ac - coupled 50 i tx /2 = v odpp /2 + (i pe /2 50) output common - mode shift i dc v od /r term output curren t that sets output level i pe C output current used for pe i tx i dc + i pe total transmitter output current v h v tto ? d v ocm + v od /2 maximum single - ended output voltage v l v tto ? d v ocm ? v od /2 minimum single - ended output voltage
d ata sheet ADN4600 rev. a | page 21 of 28 selective squelch and di sable each transmitter is equipped with disable and squelch controls. disable is a full power - down state: all transmitter current , including output current, is reduced to 0 ma and the output pins are pull ed up to vtto, but there is a delay of approximately 1 s associated with re - enabling the transmitter. the output disable control is accessed through the tx en bit (bit 5) of the tx[7:0] configuration registers through the i 2 c control interface. squelch simply reduces the output current to submicroamp level s, allowing both output pins to pull up to vtto th r ough t he output termination resistors . the transmitter recovers from squelch in less than 100 ns. the output squelch and the output disable control can both be accessed through the tx[7:0] squelch control registers, with the top nibble representing the squelch control and the bottom nibble representing the output disable for one channel. the channels are dis abled or squelched by writing 0 s to the corresponding nibbles. the channe ls are enabled by writing a ll 1 s, which is the default setting. for example, to squelch channel tx 0, register 0xc3 must be set to 0x 0f . the entire nibble must be written to all 0 s for this functionality. table 15. transmitters squelch control registers name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default tx[7:0] squelch control 0xe3, 0xeb, 0xf3, 0xfb, 0xdb, 0xd3, 0xcb, 0xc3 s quelchb [3:0] d isableb [3:0] 0x ff
ADN4600 data sheet rev. a | page 22 of 28 i 2 c control interface serial interface general functionality the ADN4600 register set is controlled through a 2-wire i 2 c interface. the ADN4600 acts only as an i 2 c slave device. therefore, the i 2 c bus in the system needs to include an i 2 c master to configure the ADN4600 and other i 2 c devices that may be on the bus. data transfers are controlled by the two i 2 c wires: the scl input clock pin and the sda bidirectional data pin. the ADN4600 i 2 c interface can be run in the standard (100 khz) and fast (400 khz) modes. the sda line only changes value when the scl pin is low, with two exceptions: the sda pin is driven low while the scl pin is high to indicate the beginning or continuation of a transfer, and the sda line is driven high while the scl line is high to indicate the end of a transfer. therefore, it is important to control the scl clock to toggle only when the sda line is stable, unless indicating a start, repeated start, or stop condition. i 2 c interface data transfers: data write to write data to the ADN4600 register set, a microcontroller (or any other i 2 c master) needs to send the appropriate control signals to the ADN4600 slave device. use the following steps, where the signals are controlled by the i 2 c master unless otherwise specified. a diagram of the procedure is shown in figure 31. 1. send a start condition (that is, while holding the scl line high, pull the sda line low). 2. send the ADN4600 part address (seven bits), whose upper five bits are the static value b10010 and whose lower two bits are controlled by the addr1 and addr0 input pins. this transfer should be msb first. 3. send the write indicator bit (0). 4. wait for the ADN4600 to acknowledge the request. 5. send the register address (eight bits) to which data is to be written. this transfer should be msb first. 6. wait for the ADN4600 to acknowledge the request. 7. send the data (eight bits) to be written to the register whose address was set in step 5. this transfer should be msb first. 8. wait for the ADN4600 to acknowledge the request. 9. send a stop condition (that is, while holding the scl line high, pull the sda line high) and release control of the bus. 10. send a repeated start condition (that is, while holding the scl line high, pull the sda line low) and continue with step 2 in this procedure to perform another write. 11. send a repeated start condition (that is, while holding the scl line high, pull the sda line low) and continue with step 2 of the read procedure (see the i 2 c interface data transfers: data read section) to perform a read from another address. 12. send a repeated start condition (that is, while holding the scl line high, pull the sda line low) and continue with step 8 of the read procedure (in the i 2 c interface data transfers: data read section) to perform a read from the same address set in step 5 of the write procedure. in figure 31, the ADN4600 write process is shown. the scl signal is shown, along with a general write operation and a specific example. in the example, data 0x92 is written to register address 0x6d of an ADN4600 part with a slave address of 0x4b. the slave address is seven bits wide. the upper five bits of the slave address are internally set to b10010. the lower two bits are controlled by the addr[1:0] pins. in this example, the bits controlled by the addr[1:0] pins are set to b11. in the figure, the corresponding step number is visible in the circle under the waveform. the scl line is driven by the i 2 c master, not by the ADN4600 slave. as for the sda line, the data in the shaded polygons of figure 31 is driven by the ADN4600, whereas the data in the nonshaded polygons is driven by the i 2 c master. the end phase case shown corresponds with step 9. it is important to note that the sda line only changes when the scl line is low, except when a start, stop, or repeated start condition is being sent, as is the case in step 1 and step 9. 1 scl sda sda g eneral case example start register addr ack ack ack stop data r/w fixed part addr addr [1:0] 2 2 3 4 5 6 7 8 9 0 7061-008 figure 31. i 2 c write diagram
data sheet ADN4600 rev. a | page 23 of 28 i 2 c interface data transfers: data read to read data from the ADN4600 register set, a microcontroller (or any other i 2 c master) needs to send the appropriate control signals to the ADN4600 slave device. use the following steps, where the signals are controlled by the i 2 c master unless otherwise specified. a diagram of the procedure is shown in figure 32. 1. send a start condition (that is, while holding the scl line high, pull the sda line low). 2. send the ADN4600 part address (seven bits), whose upper five bits are the static value b10010 and whose lower two bits are controlled by the addr1 and addr0 input pins. this transfer should be msb first. 3. send the write indicator bit (0). 4. wait for the ADN4600 to acknowledge the request. 5. send the register address (eight bits) from which data is to be read. this transfer should be msb first. the register address is kept in the ADN4600 memory until the part is reset or the register address is written over with the same procedure (step 1 to step 6 of the write procedure; see the i 2 c interface data transfers: data write section). 6. wait for the ADN4600 to acknowledge the request. 7. send a repeated start condition (that is, while holding the scl line high, pull the sda line low). 8. send the ADN4600 part address (seven bits), whose upper five bits are the static value b10010 and whose lower two bits are controlled by the addr1 and addr0 input pins. this transfer should be msb first. 9. send the read indicator bit (1). 10. wait for the ADN4600 to acknowledge the request. 11. the ADN4600 then serially transfers the data (eight bits) held in the register indicated by the address set in step 5. 12. acknowledge the data. 13. send a stop condition (that is, while holding the scl line high, pull the sda line high) and release control of the bus. 14. send a repeated start condition (that is, while holding the scl line high, pull the sda line low) and continue with step 2 of the write procedure (see the i 2 c interface data transfers: data write section) to perform a write. 15. send a repeated start condition (that is, while holding the scl line high, pull the sda line low) and continue with step 2 of the read procedure to perform a read from a another address. 16. send a repeated start condition (that is, while holding the scl line high, pull the sda line low) and continue with step 8 of the read procedure to perform a read from the same address. in figure 32, the ADN4600 read process is shown. the scl signal is shown, along with a general read operation and a specific example. in the example, data 0x49 is read from register address 0x6d of an ADN4600 part with a slave address of 0x4b. the part address is seven bits wide. the upper five bits of the slave address are internally set to b10010. the lower two bits are controlled by the addr[1:0] pins. in this example, the bits controlled by the addr[1:0] pins are set to b11. in figure 32, the corresponding step number is visible in the circle under the waveform. the scl line is driven by the i 2 c master, not by the ADN4600 slave. as for the sda line, the data in the shaded polygons of figure 32 is driven by the ADN4600, whereas the data in the nonshaded polygons is driven by the i 2 c master. the end phase case shown corresponds with step 13. it is important to note that the sda line only changes when the scl line is low, except when a start, stop, or repeated start condition is being sent, as is the case in step 1, step 7, and step 13. in figure 32, sr represents a repeated start where the sda line is brought high before scl is raised. sda is then dropped while scl is still high. 3 2 2 1 scl sda sda general case example 4 5 6 7 8 10 9 8 11 12 13 07061-009 start register addr aa asr a stop data fixed part addr fixed part addr addr [1:0] addr [1:0] r/ w r/ w notes 1. a = ack. 2. sr = a repeated start where the sda line is brought high before scl is raised. figure 32. i 2 c read diagram
ADN4600 data sheet rev. a | page 24 of 28 pcb design guideline s proper rf pcb design techniques must be used for optimal performance. power supply connections and ground planes use of one low impedance ground plane is recommended. the vee pins should be soldered directly to the ground plane to reduce series inductance. if the gr ound plane is an internal plane and connections to the ground plane are made through vias, multiple vias can be used in parallel to reduce the series inductance. the exposed pad should be connected to the vee plane using plugged vias so that solder does no t leak through the vias during reflow. use of a 10 f electrolytic capacitor between vcc and vee is recommended at the location where the 3.3 v supply enters the pcb. it is recommended that 0.1 f and 1 nf ceramic chip capacitors be placed in parallel at each supply pin for high frequency power supply decoupling. when using 0.1 f and 1 nf ceramic chip capacitors, they should be placed between the ic power supply pins (vcc, vtti, vtto) and vee, as close as possible to the supply pins. by using adjacent pow er supply and gnd planes, excellent high frequency decoupling can be attained by using close spacing between the planes. this capacitance is given by c plane = 0.88 r a/d (pf) where: r is the dielectric constant of the pcb material. a is the area of the overlap of power and gnd planes (cm 2 ). d is the separation between planes (mm). for fr4, r = 4.4 and 0.25 mm spacing, c ~15 pf/cm 2 . transmission lines use of 50 ? t ransmission lines is required for all high frequency input and output signals to minimize reflections. it is also necessary for the high speed pairs of differential input traces , as well as the high speed pairs of differential output traces, to be matched in length to avoid skew between the differential traces. soldering guidelines for chip scale package the lands on the lfcsp are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider tha n the package land width. the land should be centered on the pad. this ensures that the solder joint size is maximized. the bottom of the chip scale package has a central exposed pad. the pad on the printed circuit board should be at least as large as this exposed pad. the user must connect the exposed pad to vee using plugged vias so that solder does not leak through the vias during reflow. this ensures a solid connection from the exposed pad to vee .
d ata sheet ADN4600 rev. a | page 25 of 28 control register map table 16. basic mode i 2 c register definitions addr (hex) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default 0x00 reset reset 0x40 xpt configuration in port [ 2] in port [ 1] in port [ 0] broadcast out port [ 2] out port [ 1] out port [ 0] 0x00 0x41 xpt update update 0x00 0x50 xpt status 0 out0 [ 2] out0 [ 1] out0 [ 0] 0x51 xpt status 1 out1 [ 2] out1 [ 1] out1 [ 0] 0x52 xpt status 2 out2 [ 2] out2 [ 1] out2 [ 0] 0x53 xpt status 3 out3 [ 2] out3 [ 1] out3 [ 0] 0x54 xpt status 4 o ut4 [ 2] out4 [ 1] out4 [ 0] 0x55 xpt status 5 out5 [ 2] out5 [ 1] out5 [ 0] 0x56 xpt status 6 out6 [ 2] out6 [ 1] out6 [ 0] 0x57 xpt status 7 out7 [ 2] out7 [ 1] out7 [ 0] 0x58 xpt temp 0 out1 [ 2] out1 [ 1] out1 [ 0] out0 [ 2] out0 [ 1] out0 [ 0] 0x59 xpt temp 1 out3 [ 2] out3 [ 1] out3 [ 0] out2 [ 2] out2 [ 1] out2 [ 0] 0x5a xpt temp 2 out5 [ 2] out5 [ 1] out5 [ 0] out4 [ 2] out4 [ 1] out4 [ 0] 0x5b xpt temp 3 out7 [ 2] out7 [ 1] out7 [ 0] out6 [ 2] out6 [ 1] out6 [ 0] 0x80 rx0 configuration rx pnswap rx eqby rx en rx eq[2] rx eq[1] rx eq[0] 0x30 0x88 rx1 configuration rx pnswap rx eqby rx en rx eq[2] rx eq[1] rx eq[0] 0x30 0x90 rx2 configuration rx pnswap rx eqby rx en rx eq[2] rx eq[1] rx eq[0] 0x30 0x98 rx3 configuration rx pnswap rx eqby rx en rx eq[2] rx eq[1] rx eq[0 ] 0x30 0xa0 rx4 configuration rx pnswap rx eqby rx en rx eq[2] rx eq[1] rx eq[0] 0x30 0xa8 rx5 configuration rx pnswap rx eqby rx en rx eq[2] rx eq[1] rx eq[0] 0x30 0xb0 rx6 configuration rx pnswap rx eqby rx en rx eq[2] rx eq[1] rx eq[0] 0x30 0xb8 rx7 configuration rx pnswap rx eqby rx en rx eq[2] rx eq[1] rx eq[0] 0x30 0xc0 tx0 configuration tx en tx data rate tx pe [ 2] tx pe [ 1] tx pe [ 0] 0x20 0xc8 tx1 configuration tx en tx data rate tx pe [ 2] tx pe [ 1] tx pe [ 0] 0x20 0xd0 tx2 conf iguration tx en tx data rate tx pe [ 2] tx pe [ 1] tx pe [ 0] 0x20 0xd8 tx3 configuration tx en tx data rate tx pe [ 2] tx pe [ 1] tx pe [ 0] 0x20 0xe0 tx 4 configuration tx en tx data rate tx pe [ 2] tx pe [ 1] tx pe [ 0] 0x20 0xe8 tx 5 configuration tx en tx data rate tx pe [ 2] tx pe [ 1] tx pe [ 0] 0x20 0xf0 tx 6 configuration tx en tx data rate tx pe [ 2] tx pe [ 1] tx pe [ 0] 0x20 0xf8 tx 7 configuration tx en tx data rate tx pe [ 2] tx pe [ 1] tx pe [ 0] 0x20
ADN4600 data sheet rev. a | page 26 of 28 table 17 . advanced mode i 2 c register definitions addr (hex) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default 0x23 txheadroom txh_b3 txh_b2 txh_b1 txh_b0 txh_a3 txh_a2 txh_a1 txh_a0 0x00 0x83 rx0 eq1 control eq ctl src rx eq1 [ 5] rx eq1 [ 4] rx eq1 [ 3] rx eq1 [ 2] rx eq1 [ 1] rx eq1 [ 0] 0x00 0x84 rx0 eq3 control rx eq3 [ 5] rx eq3 [ 4] rx eq3 [ 3] rx eq3 [ 2] rx eq3 [ 1] rx eq3 [ 0] 0x00 0x85 rx0 fr4 control rx lut select rx lut fr4/cx4 0x00 0x8b rx1 eq1 control eq ctl src rx eq1 [ 5] rx eq1 [ 4] rx eq1 [ 3] rx eq1 [ 2] rx eq1 [ 1] rx eq1 [ 0] 0x00 0x8c rx1 eq3 control rx eq3 [ 5] rx eq3 [ 4] rx eq3 [ 3] rx eq3 [ 2] rx eq3 [ 1] rx eq3 [ 0] 0x00 0x8 d rx1 fr4 control rx lut select rx lut fr4/cx4 0x00 0x93 rx2 eq1 control eq ctl src rx eq1 [ 5] rx eq1 [ 4] rx eq1 [ 3] rx eq1 [ 2] rx eq1 [ 1] rx eq1 [ 0] 0x00 0x94 rx2 eq3 control rx eq3 [ 5] rx eq3 [ 4] rx eq3 [ 3] rx eq3 [ 2] rx eq3 [ 1] rx eq3 [ 0] 0x00 0x9 5 rx2 fr4 control rx lut select rx lut fr4/cx4 0x00 0x9b rx3 eq1 control eq ctl src rx eq1 [ 5] rx eq1 [ 4] rx eq1 [ 3] rx eq1 [ 2] rx eq1 [ 1] rx eq1 [ 0] 0x00 0x9c rx3 eq3 control rx eq3 [ 5] rx eq3 [ 4] rx eq3 [ 3] rx eq3 [ 2] rx eq3 [ 1] rx eq3 [ 0] 0x00 0x 9d rx3 fr4 control rx lut select rx lut fr4/cx4 0x00 0xa3 rx4 eq1 control eq ctl src rx eq1 [ 5] rx eq1 [ 4] rx eq1 [ 3] rx eq1 [ 2] rx eq1 [ 1] rx eq1 [ 0] 0x00 0xa4 rx4 eq3 control rx eq3 [ 5] rx eq3 [ 4] rx eq3 [ 3] rx eq3 [ 2] rx eq3 [ 1] rx eq3 [ 0] 0x00 0xa 5 rx4 fr4 control rx lut select rx lut fr4/cx4 0x00 0xab rx5 eq1 control eq ctl src rx eq1 [ 5] rx eq1 [ 4] rx eq1 [ 3] rx eq1 [ 2] rx eq1 [ 1] rx eq1 [ 0] 0x 00 0xac rx5 eq3 control rx eq3 [ 5] rx eq3 [ 4] rx eq3 [ 3] rx eq3 [ 2] rx eq3 [ 1] rx eq3 [ 0] 0x00 0x ad rx5 fr4 control rx lut select rx lut fr4/cx4 0x00 0xb3 rx6 eq1 control eq ctl src rx eq1 [ 5] rx eq1 [ 4] rx eq1 [ 3] rx eq1 [ 2] rx eq1 [ 1] rx eq1 [ 0] 0x00 0xb4 rx6 eq3 control rx eq3 [ 5] rx eq3 [ 4] rx eq3 [ 3] rx eq3 [ 2] rx eq3 [ 1] rx eq3 [ 0] 0x00 0x b 5 rx6 fr4 control rx lut select rx lut fr4/cx4 0x00 0xbb rx7 eq1 control eq ctl src rx eq1 [ 5] rx eq1 [ 4] rx eq1 [ 3] rx eq1 [ 2] rx eq1 [ 1] rx eq1 [ 0] 0x00 0x bc rx7 eq3 control rx eq3 [ 5] rx eq3 [ 4] rx eq3 [ 3] rx eq3 [ 2] rx eq3 [ 1] rx eq3 [ 0] 0x00 0x bd rx7 fr4 control rx lut select rx lut fr4/cx4 0x00 0xc1 tx0 output level control 1 tx0 ctl src tx0_olev1[6:0] 0x40 0xc2 tx0 output level control 0 tx0_o lev0[6:0] 0x40 0xc3 tx0 squelch control squelchb[3:0] disableb[3:0] 0xff 0xc9 tx1 output level control 1 tx1 ctl src tx1_olev1[6:0] 0x40 0xca tx1 output level control 0 tx1_olev0[6:0] 0x40 0xcb tx1 squelch control squelchb[3:0] disableb[3:0] 0xff
d ata sheet ADN4600 rev. a | page 27 of 28 addr (hex) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default 0xd1 tx2 output level control 1 tx2 ctl src tx2_olev1[6:0] 0x40 0xd2 tx2 output level control 0 tx2_olev0[6:0] 0x40 0xd3 tx2 squelch control squelchb[3:0] disableb[3:0] 0xff 0xd9 tx3 output level control 1 tx3 ctl src tx3_olev1[6:0] 0x40 0xda tx3 output level control 0 tx3_olev0[6:0] 0x40 0xdb tx3 squelch control squelchb[3:0] disableb[3:0] 0xff 0xe1 tx7 output level control 1 tx7 ctl src tx7_olev1[6:0] 0x40 0xe2 tx7 output level control 0 tx7_olev0[6:0] 0x40 0xe3 tx7 squelch control sq uelchb[3:0] disableb[3:0] 0xff 0xe9 tx6 output level control 1 tx6 ctl src tx6_olev1[6:0] 0x40 0xea tx6 output level control 0 tx6_olev0[6:0] 0x40 0xeb tx6 squelch control squelchb[3:0] disableb[3:0] 0xff 0xf1 tx5 output level control 1 tx5 ctl sr c tx5_olev1[6:0] 0x40 0xf2 tx5 output level control 0 tx5_olev0[6:0] 0x40 0xf3 tx5 squelch control squelchb[3:0] disableb[3:0] 0xff 0xf9 tx4 output level control 1 tx4 ctl src tx4_olev1[6:0] 0x40 0xfa tx4 output level control 0 tx4_olev0[6:0] 0x4 0 0xfb tx4 squelch control squelchb[3:0] disableb[3:0] 0xff
ADN4600 data sheet rev. a | page 28 of 28 package outline dimensions compliant to jedec standards mo-220-vmmd-4 0.25 min 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max seating plane pin 1 indicator 6.15 6.00 sq 5.85 pin 1 indicator 0.30 0.25 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. top view exposed pad bottom view 9.10 9.00 sq 8.90 8.85 8.75 sq 8.65 04-11-2012-b figure 33. 64-lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp-64-2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADN4600acpz ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-2 ADN4600acpz-r7 ?40 o c to +85 o c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-2 ADN4600-evalz evaluation board 1 z = rohs compliant part. ?2008C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07061-0-12/12(a)

▲Up To Search▲

Price & Availability of ADN4600

	To Download ADN4600 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .